In a CCD solid-state imaging device, CMOS-type solid-state imaging device and the like, what is called a HAD (Hole Accumulated Diode) sensor is employed, that is a structure in which a positive charge accumulated area containing P-type high impurity concentration (P+) is formed on the surface of a light-receiving sensor portion where an N-type impurity area is formed.
FIG. 16 shows a schematic sectional view of a conventional CCD solid-state imaging device employing this HAD sensor.
The CCD solid-state imaging device includes, on a semiconductor substrate 151 such as a silicon substrate, an N-type semiconductor area 152 forming a photoelectric conversion area, a P-type channel stop area (pixel-separation area) 153, a P-type semiconductor well area 154, an N-type transfer channel area 155, and a P-type reading gate 162; further, on the surface of the N-type semiconductor area 152 forming the photoelectric conversion area is formed a P+ (P-type high impurity concentration) positive charge accumulated area (Hole Accumulated Layer) 156. These N-type semiconductor area 152 and positive charge accumulated area (Hole Accumulated Layer) 156 forms a light-receiving sensor portion 161.
On the semiconductor substrate 151 is formed a charge-transfer electrode 158 through a gate insulation film.
Further, a light-shielding film 159 is formed over the charge-transfer electrode 158 through an interlayer insulation film to cover the charge-transfer electrode 158, thereby preventing noise generated in a signal charge under transfer due to light incident on a vertical transfer register 163.
The light-shielding film 159 has an opening above the light-receiving sensor portion 161 so that light can be incident on the light-receiving sensor portion 161.
The P-type semiconductor well area 154, N-type transfer channel area 155, and charge-transfer electrode 158 above these areas form a vertical transfer register 163. The charge-transfer electrode 158 is formed ranging from the vertical transfer register 163 to the reading gate 162.
The vertical transfer register 163 is provided on one side of the light-receiving sensor portion 161 arranged in a vertical direction (the direction perpendicular to the surface of paper in FIG. 16), and has a belt-like plane shape. A horizontal transfer register, not shown, is connected to one end of the vertical transfer register 163.
Further, the channel stop area (pixel-separation area) 153 is formed between the light-receiving sensor portions 161 in the vertical direction, thereby causing the light-receiving sensor portion 161 of each pixel to be separated.
In this way, a plurality of light-receiving sensor portions 161 are arranged like a matrix and form the CCD solid-state imaging device (See, for example, Patent Literature 1 cited below)
In such solid-state imaging device, a single layer or a plurality of layers of the charge-transfer electrode 158 made of polycrystalline silicon or the like are usually formed on the reading gate 162 and vertical transfer register 163.
The potential of the reading gate 162 and the potential of the vertical transfer register 163 are controlled to read the signal charge from the light-receiving sensor portion 161 (particularly from the photoelectric conversion area 152 thereof) to the vertical transfer register 163 and to transfer the signal charge in the vertical transfer register 163.
On this occasion, the potential of the channel stop area (pixel-separation area) 153 is controlled so that the charge may not be read into adjacent pixels in a horizontal direction, that is, a lateral direction in the drawing.
The incident light is converted to the signal charge and is stored in the photoelectric conversion area (N-type semiconductor area) 152.
However, reduction in pixel size has been advanced in recent years, so that the solid-state imaging device may not make normal operation with the conventional structure of the impurity area.
Specifically, with the reduction of pixel size, the respective potentials of the channel stop area (pixel-separation area) 153, vertical transfer register 163, reading gate 162, and photoelectric conversion area (N-type semiconductor area) 152 are mutually affected by the two-dimensional modulation; thus, it has become difficult to maintain the blooming characteristic, readout characteristic, pixel-separation characteristic, and noise characteristic on the same level as before.
If the width of the reading gate 162 becomes narrower for example, the potential of the reading gate 162 is affected by the vertical transfer register 163 and photoelectric conversion area 152 to make the potential of reading gate 162 lower. This causes deterioration of the blooming characteristic. When the potential of the photoelectric conversion area 152 is made deeper to prevent this point, a voltage for reading must be made high, and therefore a charge-readout characteristic will deteriorate.
Further, if the channel stop area (pixel-separation area) 153 is made narrower for example, similarly to the potential of the reading gate 162, the potential thereof is affected by the two-dimensional modulation and becomes lower with the result that the pixel-separation characteristic will deteriorate.
Furthermore, because it becomes difficult to maintain a characteristic on the amount of saturated signal with reduction in the size of photoelectric conversion area 152, the photoelectric conversion area 152 must be made shallower; in that case, the potential of the positive charge accumulated area (Hole Accumulated Layer) 156 on the surface of the photoelectric conversion area 152 becomes lower, which makes lower the probability of trapping electron, that is, a noise component against holes and so causes an increase of the noise component.
When the concentration of P-type impurity in the positive charge accumulated area (Hole Accumulated Layer) 156 is increased to prevent this point, the potential of the adjacent reading gate 162 goes high to deteriorate the readout characteristic. At the same time, the potential of the channel stop area (pixel-separation area) 153 also goes high and an electric field between the channel stop area (pixel-separation area) 153 and vertical transfer register 163 is intensified at the time of reading charge, assumedly making the noise component increase due to avalanche breakdown and the like.
To cope with the above-described problems, the following method has been devised; the depth of each potential of the channel stop area (pixel-separation area) 153, reading gate 162, and positive charge accumulated area (Hole Accumulated Layer) 156 is made variable, for example, by applying a predetermined voltage signal to the light-shielding film 159, and for example, when the blooming characteristic, pixel-separation characteristic, and noise characteristic deteriorate, a minus voltage signal is applied to the light-shielding film 159, and when the readout characteristic deteriorates, a plus voltage signal is applied to the light-shielding film 159, thereby allowing the blooming characteristic, readout characteristic, pixel-separation characteristic, and noise characteristic to be secured satisfactorily (See, for example, Patent Literature 2 cited below).
(Patent Literature 1)    Published Japanese Patent Application No. 2002-252342 (Paragraph No. [0021], FIG. 3)
(Patent Literature 2)    Published Japanese Patent Application No. 2002-51267
Further, in an IT (interline)-type solid-state imaging device, for the purpose of restricting smears, a metal light-shielding film made of aluminum or the like is formed over the whole surface except the opening of photoelectric conversion area (See, for example, Patent Literature 3 cited below). That light-shielding film is usually connected to the ground (GND).
(Patent Literature 3)    Published Japanese Patent Application No. 2001-345437 (pp. 3-4, FIG. 1)
However, in the CCD solid-state imaging device shown in FIG. 16, when it is designed that a voltage signal is applied to the light-shielding film 159, it may be difficult to satisfy both of the noise characteristic and readout characteristic, depending on a design condition of each part (width, depth, impurity concentration, and the like).
This is because the light-shielding film 159 is formed projecting above the P+ positive charge accumulated area (Hole Accumulated Layer) 156 on the surface of the light-receiving sensor portion 161 in order to prevent the incidence of light on the vertical transfer register 163 as described above.
With this, for example, in the case where the potential of the positive charge accumulated area (Hole Accumulated Layer) 156 is raised by applying a minus voltage signal to the light-shielding film 159 to enhance the probability of trapping electron, that is, the noise component against holes and thereby improves the noise characteristic, an intense electric field is generated between the N-type transfer channel area 155 and P+ positive charge accumulated area (Hole Accumulated Layer) 156 on the side of the channel stop area (pixel-separation area) 153, or between the N-type semiconductor area 152 and P+ positive charge accumulated area (Hole Accumulated Layer) 156; thus, there may occur a lot of noise components due to avalanche breakdown or the like, which makes obtaining a sufficient noise characteristic difficult.
On the other hand, also on the side of reading gate 162, there is a possibility that the potential of the reading gate 162 is raised by applying the minus voltage signal to the light-shielding film 159, which makes the reading voltage increase to cause a readout characteristic to be obtained insufficiently.
Further, if P-type impurity concentration contained in the positive charge accumulated area (Hole Accumulated Layer) 156 is reduced for example, then the readout characteristic improves, but the noise characteristic deteriorates.
Furthermore, if a unit pixel size of the solid-state imaging device is reduced, when a P+ layer of the positive charge accumulated area (Hole Accumulated Layer) is formed, the P+ layer will diffuse under a reading electrode and a transfer electrode forming the sensor opening, being affected by an ion-implantation method, heat-treatment method and the like. This makes a unfavorable effect on a sensor characteristic.
For example, as shown in FIG. 28, when a P+ layer 216 of a sensor portion 214 diffuses under an electrode 212 (toward a reading gate 221 under an electrode 212R), the reading voltage rises and a dynamic margin to a driving voltage decreases. Further, when the P+ layer 216 diffuses under an electrode 212 (transfer electrode 212T) of the vertical register on the side of an adjacent pixel in a horizontal direction, an effective area of the vertical register 231 is reduced and the amount of electric charge handled by the vertical register 231 decreases.
To cope with this point, in the case where ion implantation when forming the P+ layer 216 is performed such that P-type impurities are ion-implanted using a mask or the like so as to keep away from the end of the opening of the sensor portion 214, the pinning on the surface of the sensor portion 214 is weakened and a dark current increases, and therefore a defect when there is no incident light (a so-called white noise) increases. Therefore, it is desired that the P+ layer 216 is formed not to go under the electrode 212 made of the reading electrode and transfer electrode, but to be adjacent to the end of the electrode 212; however, practically it is difficult because P-type impurities are diffusive.
In order to overcome the above-described problems, the present invention provides a solid-state imaging device having a sufficient noise characteristic and readout characteristic by improving the noise characteristic and readout characteristic in a well-balanced manner, as well as a method of manufacturing the same.
Further, the present invention provides a solid-state imaging device of high quality and a driving method thereof, as well as a method for manufacturing thereof, capable of enhancing the pinning of the sensor portion to reduce a dark current and decrease the white noise at a dark time.